--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:16:52 12/02/2013
-- Design Name:   
-- Module Name:   H:/My Documents/Wery Punny Prochect/linesearcher/linesearcher_tb.vhd
-- Project Name:  linesearcher
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: marsrover
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY marsrover_tb IS
END marsrover_tb;
 
ARCHITECTURE behavior OF marsrover_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT marsrover
    PORT(
          clk : in std_logic;
    
          sensor_l : in std_logic;
          sensor_m : in std_logic;
          sensor_r : in std_logic;
          reset : in std_logic;
          reset_io : in std_logic;
   
          do_cross : in std_logic;
		      do_search : in std_logic;
    
          motor_l : out std_logic; 
          motor_r : out std_logic;
	        debug_led_1 : out std_logic;
		      debug_led_2 : out std_logic;

		      display_data	: out	std_logic_vector (7 downto 0);
		      display_enable	: out	std_logic_vector (3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal sensor_l : std_logic := '0';
   signal sensor_m : std_logic := '0';
   signal sensor_r : std_logic := '0';
   signal reset : std_logic := '0';
   signal reset_io : std_logic := '0';
   signal do_cross : std_logic := '1';
   signal do_search : std_logic := '1';

 	--Outputs
   signal motor_l : std_logic;
   signal motor_r : std_logic;
   signal display_data : std_logic_vector(7 downto 0);
   signal display_enable : std_logic_vector(3 downto 0);
	 signal sensor : std_logic_vector(2 downto 0);
	 signal led1, led2 : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: marsrover PORT MAP (
          clk => clk,
          sensor_l => sensor_l,
          sensor_m => sensor_m,
          sensor_r => sensor_r,
          reset => reset,
          reset_io => reset_io,
          do_cross => do_cross,
          do_search => do_search,
          motor_l => motor_l,
          motor_r => motor_r,
          display_data => display_data,
          
 	        debug_led_1 => led1,
		      debug_led_2 => led2,
          display_enable => display_enable
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
	sensor_l <= sensor(2);
	sensor_m <= sensor(1);
	sensor_r <= sensor(0);

	reset <= '1' after 0 ns,
	         '0' after 100 ns,
	         '1' after 900 ns,
	         '0' after 1000 ns,
	         '1' after 2900 ns,
	         '0' after 3000 ns;
	         
	reset_io <= '1' after 0 ns,
	         '0' after 100 ns,
	         '1' after 900 ns,
	         '0' after 1000 ns,
	         '1' after 2900 ns,
	         '0' after 3000 ns;	         
	         
	         
	sensor <= "111" after 0 ns, ---nocross, nosearch
	          "101" after 200 ns, --straight
	          "111" after 300 ns;
	    
	          
	          

	          
	          
	 do_search <= '1' after 0 ns,
	              '0' after 3000 ns,
	              '1' after 5000 ns;
	              
	 do_cross <= '1' after 3000 ns,
	              '0' after 13000 ns;			
			

END;



